1. Field of the Invention
This invention relates to circuits for buffering multiple data streams. More particularly, this invention relates to a multiport, multiformat cache memory that queues incoming data to be stored in a DRAM and queues outgoing data retrieved from the DRAM.
2. Discussion of the Related Art
Multimedia applications for personal computers have proliferated in the last few years. Some multimedia applications require that a personal computer process data that represents text, graphics, still images, audio, and full-motion video. Video data requires high speed processing systems and a large frame buffer memory, usually a DRAM, to temporarily store the incoming video data prior to the data being displayed on a video screen or captured on a hard disk. In some high resolution video systems, a 4 megabyte DRAM is needed to store a single frame of video data.
FIG. 1A illustrates a typical multimedia application in which it is desirable that two asynchronous input data streams 102 and 104 be stored in a DRAM 108 to be retrieved for processing (e.g., display) at a later time. These two input data streams 102 and 104 (labeled as VIN1 and VIN2) are stored in DRAM 108 under control of a DRAM Control 106. At a later time, the data must be retrieved from DRAM 108 by DRAM Control 106 and supplied to either or both of output data terminals 110 and 112 (labelled as VOUT and CAP). VOUT may lead to circuitry for directly displaying the outputted data on a video screen, while CAP (capture) may lead to circuitry for storing the data on a hard disk.
Importantly, prior to storage in DRAM 108, it is usually necessary for the incoming data streams 102 and 104 to be buffered (i.e., queued) due to differences between the rates of the incoming data input streams and the rate at which the DRAM stores the two data streams. For example, since the DRAM may have only a single data input port, it may be desirable for the DRAM to store a block of data from one data stream at a time at a high burst rate, while additional data from the two data streams continue to be incoming. Buffering is typically performed using a number of First In - First Out (FIFO) memories, as shown in FIG. 1B. The reason for using FIFO's is to allow multiple sources to share a single DRAM. The FIFO's allow a continuous stream of data to be temporarily stored while another source accesses the DRAM. The FIFO's also increase the available bandwidth of the DRAM by allowing back-to-back cycles to be bursted (page mode). Finally, FIFO's allow asynchronous systems to communicate with one another.
In FIG. 1B, input data stream 102 (labelled as VIN1) is queued in a FIFO 114, controlled by Control 116, prior to being stored in DRAM 108, controlled by DRAM Control 106. FIFO 114 could be a fall-through type FIFO which successively moves a word through each register of the FIFO.
Input data stream 104 (labelled as VIN2) is queued by a FIFO 118, controlled by a Control 120, prior to being stored in DRAM 108.
Output data stream 110 (labelled VOUT) is queued by a FIFO 132, controlled by a Control 134, prior to being displayed on a video screen. And, output data stream 112 (labelled CAP) is queued by a FIFO 142, controlled by a Control 144, prior to being captured on a hard disk.
The prior art storage scheme illustrated by FIG. 1B has several disadvantages. For example, each FIFO 114, 118, 132 and 142 must be large enough in storage capacity to handle the longest (worst case) data burst anticipated for the data stream. For video applications, significant FIFO buffer sizes are required for each data stream in the system. This takes up valuable silicon real estate. Furthermore, the physical size of the data lines into and out of each of the FIFOs can be significant and in some cases redundant. Such data lines result in unnecessary congestion in the physical layout of the system. Finally, replication of FIFO control circuitry for each individual FIFO adds redundant elements to the overall system.